1. Field of the Invention
The present invention relates to a twin well formation method for a semiconductor device, and in particular to an improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess problem which occurs due to the capacitor.
2. Description of the Conventional Art
Conventionally, a diffusion twin well formation method is directed to developing a relatively thick oxide film on an n-well surface of a substrate, and to forming a well in a self-aligning twin tub with one mask of the thick oxide film which is used as a masking layer during a p-type ion implantation doping process.
FIGS. 1A through 1E show a CMOS twin well formation method in the prior art.
As shown in FIG. 1, a thermal oxide film 12 is developed on a p-type silicon substrate 10 to have a thickness of 100 .ANG., and a Si.sub.3 N.sub.4 of a silicon nitride film 14 is developed on the thermal oxide film 12 in an LPCVD method to have a thickness of 1400 .ANG..
Thereafter, the silicon nitride film 14 is etched with a mask of a photoresist film pattern 16 so as to define an n-well region, and a pattern as shown in FIG. 1B is formed. Phosphorus of 1.0.times.10.sup.13 ions/cm.sup.2 is implanted into the n-well region, and the photoresist pattern 16 is removed, and an annealing process is performed at an environment of 900.degree. C. and H.sub.2 /O.sub.2 so as to develop n-well drive-in and thermal oxide film.
As a result, as shown in FIG. 1C, an n-well 18 is formed within the silicon substrate, and an oxide film 20 having a thickness of 4500 .ANG. is formed on the n-well 18.
Thereafter, as shown in FIG. 1D, the silicon nitride film 14 of a region, on which a p-well is formed, is removed by dipping it into a hot H.sub.3 PO.sub.4 liquid, and boron which is in an environment of 5.0.times.10.sup.12 ions/cm.sup.2 and 80 KeV is implanted into a certain region in which the thick oxide film is not formed, and is annealed at an environment of N.sub.2 for 4 hours, and a p-well 22 is formed within the silicon substrate.
At this time, the oxide film 20 having a thickness of 4500 .ANG. formed on the n-well 18 is used as an ion implantation mask during a formation of a p-well 22.
Thereafter, as shown in FIG. 1E, the thermal oxide films 12 and 20 are concurrently removed by dipping into HF, and the well formation process is finished. Since the following process thereof is the same as a conventional well-known CMOS device fabrication process, the description thereof will be omitted.
As a result of the above-mentioned process, since the thickness of an oxide film, which is developed when forming an n-well, is about 4000 .ANG., even though half of the thickness of the substrate is referred to the thickness of the developed oxide film, the recess "d" between the p-well 22 and the n-well 18 is about 2000 .ANG..
Therefore, in terms of the high integrated device, the following problem generally occur. First, the spacer at a well boundary is increased due to the dopant compensation at a boundary between the n-well and the p-well. Second, the reliability of the device is decreased because of the increased recess between the n-well and the p-well.
In more detail, regarding the spacer development at a well boundary, since the diffusion of the phosphorus dopant of the n-well is increased during the LOCUS process which is directed to annealing the n-well, the boundary is expanded more compared with the n-well boundary at its initial stage. In addition, the p-well becomes adjacent to the n-well since the oxide film on the n-well acts as a boundary between the oxide film and the n-well.
In this regard, the dopant compensation phenomenon occurs in the boundary between the n-well and the p-well during a diffusion process, and it is impossible to control the density of doping. As a result, the real doping density is decreased. That is, the dead spacer between the n-well and the p-well, in which the spacer is not used for the active region of a device, is increased.
Generally, in order to secure the desired latch-up characteristic between the n-well and the p-well, it is necessary to obtain a substantial spacer between wells. However, with the above-mentioned processes, since the dead spacer is increased, the layout scaling for the device of a high integration density has some problems.
Next, regarding the reliability decrease, which is caused due to the recess increase between the n-well and the p-well, since the CMOS twin well of a twin tub construction, which is fabricated in a self aligning process of the conventional LOCUS method, has recesses between the lowered n-well region and the p-well region, different thickness is formed with respect to the PR when depositing a photoresist film with respect to the photolithography process within a certain boundary between the n-well and the p-well.
Generally, when developing the LOCUS oxide film having a thickness of 4000 .ANG. on the n-well, the thickness at the well boundary varies within a range of 10 .mu.m.
Since the pattern dimension exceeds 1.0 .mu.m in the part, that is, the variation of the dimension is within a range of 10% of the pattern width, there is no problem in fabricating the device. As the device becomes high-integrated, the pattern having a width of below 1.0 is required. When the width of the pattern variation is within a range of 0.1 .mu.m, the general error tolerance exceeds 10%, so that it is impossible to design a critical circuit sensitive to the process variation to be within a range of 10 .mu.m.
This limitation becomes a handicap in designing a circuit for the latch-up suppression, so that it is difficult to fabricate a desired device.
The recess of the well region becomes a more serious problem to the DRAM device of which a capacitor is mounted within the p-well region. Referring to FIG. 2A, the reason will now be explained.
The DRAM device having a CMOS twin well structure is generally directed to dispose a memory cell 28 in the p-well 22 and a related driving circuit 30 in the n-well 18. In addition, the capacitor 26 is mounted on the p-well 22 having a recess higher than that of the n-well 18.
Therefore, after forming a capacitor, in the back-end process, the recess difference between the memory cell region (p-well region) 28 and the peripheral circuit region (n-well region) 30 is increased. Generally, the recess difference "d'" between the memory cell region 28 and the peripheral circuit region 10 exceeds 1000 .ANG..
As described above, when the recess difference becomes great, since the depth of focus (DOF) of the aligner in the photolithography of the contact formation step and the line patterning step departs from its limitation, the critical dimension is not properly controlled. The region in which the depth of focus is beyond the limitation is not properly etched, and the existence remains there, so that a desired wiring pattern cannot be achieved.
This phenomenon becomes more serious due to the variation of pattern width which is caused by the recess, so that the characteristic of a device is deteriorated.
Therefore, in order to overcome the above-mentioned problems, it is required to add an etch-back global process, before a wiring process, which is characterized to depositing a CVD film and etching-back due to a topology recess exceeding the range of the depth of focus even though the method is complex for the mass-production.
In addition, in order to achieve a constant capacitance same as the conventional level in the capacitor region in which the density level of the DRAM device is sharply increased and decreased, a single stack capacitor is adopted instead of the multi-stack capacitor or a cylindrical structure. Therefore, the recess difference between the n-well and the p-well is increased, this becomes a serious problem.
Therefore, in the industry, studies are intensively conducted in order to minimize the recess difference between the n-well and the p-well in the DRAM device of the next CMOS structure.
For example, Hitachi co. introduced a 256 Mb DRAM device as shown in FIG. 2B, which is directed to oxidize the p-well region before forming well, removing the oxide film, and recessing the substrate of the p-well region in advance, the substrate of the n-well region 22 after forming the well compensates the recess difference which are formed the recesses, so that the recess difference "d'" between the memory cell region 28 and the periphery circuit 30.
However, since the above-described method improves only the recess difference as much as the recessed p-well, the reliability of wiring in a fabrication cost increase, a contact of a high aspect ratio, and a high topology is decreased.